The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure having improved junction resistance and contact resistance, and containing a vertical Schottky contact transistor located on a substrate, and a method of forming the same.
Vertical transistors are an attractive option for technology scaling for 5 nm and beyond technologies. Vertical transistors have a channel oriented perpendicular to the substrate surface, as opposed to being situated along the plane of the surface of the substrate in the case of a lateral transistor. By using a vertical design, it is possible to increase packing density. That is, by having the channel perpendicular to the substrate, vertical transistors improve the scaling limit beyond lateral transistors.
Access resistance of the contact to the bottom source/drain structure to the vertical channel is one major problem for performance gain hoped for in a vertical transistor. As such, there is a need for providing a vertical transistor in which the access resistance problem mentioned above is circumvented to at least some degree.